Cambridge SystemVerilog Tutor

Getting Started

Welcome to the Cambridge SystemVerilog Tutor. This is a resource for students to learn the basics of SystemVerlog. It is aimed at people with little or no knowledge of hardware description languages and should be adequate preparation for the Part-1b ECAD laboratory exercises.


Cambridge Users:


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For users with raven accounts, no registration is nessesary. Just log in and get started.

External Users:


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Site information

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